The present invention relates to integrated circuit design, and more specifically, to boundary assertion-based power recovery in integrated circuit design.
The process of developing an integrated circuit (i.e., chip) involves a number of phases such as the logic design, physical synthesis, routing, and manufacture. Each of the phases can include multiple processes that may be performed iteratively. In addition to the functional requirements for the chip, the design and subsequent physical implementation must typically conform to timing and power consumption constraints. Timing and power requirements can require a balancing because larger logic gates or gates with lower voltage thresholds, which generally perform faster and improve timing, tend to consume more power. Generally, power recovery is performed after timing optimization on components with positive timing slack (i.e., components that exceed the timing requirement). The timing analysis and optimization can be performed hierarchically by subdividing the complete integrated circuit (e.g., into cores of units that each include macros). Timing analysis for each subdivision (e.g., core, unit, macro) is facilitated by boundary assertions that specify the requisite information at the input pins (PIs) of the subdivision. When the boundary assertions are unnecessarily pessimistic, the design of each subdivision tends to become over-optimized. In this case, power usage is beyond that which is actually required to meet the timing constraints for the chip.